In recent years, research and development has been actively conducted on devices using organic semiconductors. Among such devices, organic electroluminescence (EL) devices are being put into practical use as display units. Organic field-effect transistors (FETs) using an organic semiconductor as an active layer have also been drawing public attention as a useful switching element. These devices using organic semiconductors are advantageous because the organic semiconductor can be obtained by a printing process at a low temperature, costs can be reduced, etc. Furthermore, such a device can be fabricated on a plastic or like flexible substrate, and it offers mechanical flexibility. Therefore, applications that differ from those of devices using conventional inorganic semiconductors are expected to be found by using these advantages.
An organic FET is equipped with three electrodes, i.e., a gate, a source, and a drain, in the same manner as a device in which an inorganic semiconductor is used. In an FET, the electric current across the drain and source electrodes is controlled by applying voltage to the gate electrode. However, since the organic semiconductor is less conductive than the inorganic semiconductor, an organic FET has fewer carriers induced in its active layer. Therefore, in order to form a channel in the active layer, it is necessary to inject carriers from the drain electrode and the source electrode.
In order to facilitate the injection of carriers from the drain electrode and the source electrode, an organic FET having interface layers (admolecule layers) each between an active layer and a drain electrode and between an active layer and a source electrode has been proposed (for example, see Patent Document 1). FIG. 8 shows a cross-sectional view of a prior-art organic FET disclosed in Patent Document 1.
A method for fabricating a prior-art organic FET is explained below with reference to FIG. 8. First, a 100-nm-thick film is formed on an insulating substrate 101 formed from a glass substrate by sputtering chromium, and then a gate electrode 102 is formed by photolithography. Second, a 300-nm-thick SiN layer is formed by CVD (chemical vapor deposition), and then a gate insulating film 103 is formed. Subsequently, after forming a resist pattern having an edge with an inverse-tapered shape, 1-nm-thick chromium and 100-nm-thick gold layers are sequentially deposited on the resist pattern, and a source electrode 104 and drain electrode 105 are formed by a lift-off method. Third, the resulting laminate is immersed into a 0.1 mMol/l octadecanethiol solution for 1 minute, and then an admolecule layer 701 is formed on the surfaces of the source electrode 104 and the drain electrode 105. The admolecule layer 701 has a structure wherein sulfur atoms are adhered to the electrode surfaces, and octadecanethiol molecules, which are obtained by desorbing the H in the mercapto group in octadecanethiol, are oriented to the surfaces of the electrodes. In the last step, a 50-nm-thick pentacene is evaporated in an atmosphere of 2.7×10−4 Pa at a rate of 0.1 nm/s to form a semiconductor layer 106 that covers the gate insulating film and the admolecule layer.
The operation of the admolecule layer 701 in the organic FET is as follows. By forming the admolecule layer 701 on the surfaces of the source electrode 104 and the drain electrode 105, the water repellence of the electrode surface is improved and the grain of the semiconductor layer 106 is enlarged. If the immersion time is extended from one minute to one day, the contact angle used as a water-repellence index will change from 95° to 101°. When the immersion time is set to one day in order to improve the water repellence of the electrode surface, the electric current across the drain electrode and the source electrode is decreased by two orders of magnitude compared to an organic FET without the admolecule layer 701. This is because the thickness of the admolecule layer 701 is increased to approximately 2.3 nm, and the efficiency of carrier injection from the source electrode 104 to the semiconductor layer 106 via the admolecule layer 701 is decreased. When the immersion time is shortened to one minute, the thickness of the admolecule layer 701 will become 1 nm or less, and the carrier injection efficiency from the source electrode 104 to the semiconductor layer 106 will be improved. As is clear from the above, by placing an admolecule layer with a desirable thickness between a semiconductor layer and a source electrode and between a semiconductor layer and a drain electrode, the electric current across the drain electrode and the source electrode is increased. In other words, by employing the technique of Patent Document 1, the thickness of the admolecule layer is decreased by shortening the immersion time, and therefore the carrier injection efficiency is improved.
Patent Document 2 is related to the above-described technique.
[Patent Document 1] Japanese Unexamined Patent Publication No. 2005-93542 (in particular, pages 7 to 9)
[Patent Document 2] Japanese Unexamined Patent Publication No. 2005-223107 (in particular paragraph 0023)